Integrated circuit memory devices can be classified into two groups: nonvolatile memory devices and volatile memory devices. In a nonvolatile memory device, data is stored in a memory cell including a floating gate and a control gate. The floating gate includes a tunnel oxide layer on a semiconductor substrate, and the control gate includes an oxide/nitride/oxide (ONO) layer formed on the floating gate.
A nonvolatile memory cell typically performs three operations: erase operations, program operations, and read operations. Program operations can be performed by charging the floating gate with electrons. In particular, the floating gate can be charged through hot channel electron injection by applying a voltage of approximately 6 V to 7 V to the drain and applying a higher voltage on the order of 12 V to the gate. Erase operations can be performed by grounding (Vg=0 V) the gate and applying a relatively high voltage on the order of a 12 V supply voltage to the source. These conditions may generate Fowler-Nordheim (F-N) tunneling to the source, thereby discharging electrons from the floating gate. Read operation can be performed by detecting an "ON" or "OFF" state of the memory cell by detecting a current flowing through the memory cell.
Peripheral circuit transistors are generally required in a nonvolatile memory device to perform the above mentioned erase, program, and read operations. These peripheral circuit transistors may include a low voltage PMOS transistor, a high voltage NMOS transistor, and a low voltage NMOS transistor. FIGS. 1A through 1F are cross sectional views illustrating steps of a method for forming a high voltage NMOS transistor, a low voltage NMOS transistor and a low voltage PMOS transistor for a peripheral circuit of a conventional nonvolatile memory device.
As shown in FIG. 1A, an N-well 10 and a P-well 12 are formed in the P-type semiconductor substrate 14. A low voltage PMOS transistor will be formed on the N-well 10, a low voltage NMOS transistor will be formed on the P-well 12, and a high voltage NMOS transistor will be formed on the P-type semiconductor substrate 14. A pad oxide layer and a nitride layer are formed on the substrate covering the N-well and P-well, and these layers are patterned to form the pad oxide layers 16 and the nitride layers 18 which cover active regions of the substrate. A patterned photoresist layer 20 is then formed exposing the P-well 12 and covering the N-well 10 and the P-type semiconductor substrate 14. P-type dopants 22, such as boron, are then implanted using the patterned photoresist layer 20 and the nitride layer 18 as masks to form an N.sup.- channel stopper 24.
The first patterned photoresist layer 20 is then removed, and a second patterned photoresist layer 26 is formed on the substrate. The second patterned photoresist layer exposes portions of the P-type semiconductor substrate 14 spaced apart from the nitride layer 18, as shown in FIG. 1B. P-type dopants 28, such as boron atoms, are implanted using the second patterned photoresist layer 26 as a mask to form an N.sup.- channel stopper 30. The photoresist layer 26 extends beyond the nitride layer 18 over isolation regions of the P-type substrate 14 by a distance d. Accordingly, even if the high voltage NMOS transistor is subsequently formed with a double diffused drain (DDD) structure in which an N.sup.- layer completely surrounds an N.sup.+ layer, the N.sup.- layer will be spaced apart from the N.sup.- channel stopper 30 by a predetermined distance. Because a breakdown voltage of a transistor can be increased, the method discussed above is widely used in the design of peripheral circuits using high voltages.
After removing the second patterned photoresist layer 26, a field oxide layer 32 is formed by oxidizing portions of the substrate exposed by the patterned nitride layer 18, and the nitride layer 18 and the oxide layer 16 are removed, as shown in FIG. 1C. Gate oxide layers 34 of the low voltage PMOS transistor and the low voltage NMOS transistor and a gate oxide layer 36 of the high voltage NMOS transistor are then formed. As shown, the gate oxide layer 36 of the high voltage transistor is thicker than the gate oxide layers 34 of low voltage transistors. The gate electrodes 38 are then formed on the respective gate oxide layers 34 and 36, and a third patterned photoresist layer 40 is formed exposing the active region of the substrate where the low voltage PMOS transistor is to be formed. P-type dopants 42 are then implanted at a relatively high concentration into the exposed active regions of the substrate to provide P.sup.+ source/drain regions 43 for the low voltage PMOS transistor.
After removing the third patterned photoresist layer 40, a fourth patterned photoresist layer 44 is formed exposing an area where the low voltage NMOS transistor is to be formed, as shown in FIG. 1D. N-type dopants 46 are then implanted with an energy of approximately 40.about.60 KeV at a dose of 5.times.10.sup.12 .about.1.times.10.sup.13 cm.sup.-2 using the fourth patterned photoresist layer 44 and the gate electrode 38 as implant masks to form the N.sup.- source/drain regions 48 of the low voltage NMOS transistor.
After removing the fourth patterned photoresist layer 44, oxide spacers 49 are formed along the sidewalls of each gate electrode 38, as shown in FIG. 1E. A fifth patterned photoresist layer 50 is then formed exposing an area where the low voltage NMOS transistor is to be formed. N-type dopants 52 are implanted with an energy of approximately 40.about.80 KeV at a dose of approximately 5.times.10.sup.15 cm.sup.-2 using the fifth patterned photoresist layer 50, the gate electrode 38, and the spacers 49 as implant masks to form second N.sup.+ source/drain regions 54 for the low voltage NMOS transistor. The low voltage NMOS transistor having the LDD structure is thus complete.
After removing the fifth photoresist pattern 50, a sixth patterned photoresist layer 56 is formed exposing an area where the high voltage NMOS transistor is to be formed, as shown in FIG. 1F. N-type dopants 58, such as Phosphorus (P) and arsenic (As) ions, are simultaneously implanted using the sixth patterned photoresist layer 56, the gate electrode 38, and the spacers 49 as implant masks. In particular, the phosphorus (P) ions can be implanted at a dose of approximately 1.times.10.sup.14 .about.1.times.10.sup.15 cm.sup.-2 and the arsenic (As) ions can be implanted at a dose of approximately 5.times.10.sup.15 cm.sup.-2, with an energy of approximately 100 KeV. If a high temperature anneal is then performed, the phosphorus (P) ions may diffuse more rapidly, thereby completing a high voltage NMOS transistor with a double diffused drain (DDD) structure in which the N.sup.- phosphorous dopant region 62 completely surrounds the N.sup.+ dopant region 60.
According to the method discussed above, the second patterned photoresist layer 26 determines a spacing between the N.sup.- impurity region 62 of the high voltage NMOS transistor and the P.sup.- channel stopper 30. Accordingly, it may be necessary to form the second patterned photoresist layer in addition to the first patterned photoresist layer to provide a desired spacing. In addition, separate steps may be needed to form the source/drain regions for the high voltage NMOS transistor with the DDD structure and to form the source/drain regions for the low voltage NMOS transistor. This method may be further complicated in that a step of forming a sixth patterned photoresist layer 56 may be required when forming the high voltage NMOS transistor having the DDD structure. Furthermore, the N.sup.- region 62 for the high voltage NMOS transistor may diffuse laterally thus degrading a punchthrough characteristic of the transistor.
In a conventional nonvolatile memory device, however, a source leakage current may increase due to parasitic holes when a high voltage of about 12 V is applied to a source during an erase operation. The erase operation may thus make it difficult scale a memory cell down to a submicron level. The increase in the leakage current due to the generation of hot holes can be reduced by applying a negative bias to a gate during erase operations. In order to apply the negative bias to the gate, a high voltage PMOS transistor may be required in the peripheral circuit. Methods of forming a high voltage PMOS transistor in the peripheral circuit having the conventional low voltage PMOS transistor, high voltage NMOS transistor and low voltage NMOS transistor have thus been proposed. The method of manufacturing the peripheral circuit for a nonvolatile memory device having such a high voltage PMOS transistor is similar to that shown in FIGS. 1A through 1F.
Because the peripheral circuit for the nonvolatile memory device may require a step of forming a patterned photoresist layer when forming a P.sup.- channel stopper for the high voltage PMOS transistor and a step of forming another patterned photoresist layer when forming a source/drain region of the high voltage PMOS transistor, the fabrication process may become more complex. In addition, the N.sup.- impurity region of the high voltage NMOS transistor may laterally diffuse, thereby degrading a punchthrough characteristic.